                         80C166 Microcontroller FAQ

                   Trademarks belong to their owners ;-)

This is the 80C166 Microcontroller FAQ - Frequently Asked Questions around
the 80C166 family by Siemens and ST10 family by SGS-Thomson are answered
with this document.

This FAQ is maintained by:

                         Olaf 'Olu' Pfeiffer, Hitex

The original of this FAQ is kept in HTML. It includes block diagrams which
are NOT available with the ASCII version. I highly recommend
reading/browsing the HTML version!

This FAQ can be found on the servers/mirrors of the FAQ Library
www.faqlib.com

Feel free to send your comments or corrections, error reports or other
contributions to 80c166faq@hitex.com.

Thank you to Ruediger Deppe for providing a postscript version of this FAQ.
It is available as 80c166.ps.

---------------------------------------------------------------------------

Contents

        o ABOUT THIS FAQ
             + Who put this FAQ together?
             + How can I contribute to this FAQ?
             + What newsgroups will this FAQ be posted to?
             + May I distribute this FAQ or post it somewhere else?
             + How about FAQs on other microcontrollers?
        o ABOUT THE 80C166
             + The 80C166 Microcontroller - Overview
             + Registers, Context Pointer (CP)
             + Address Space
             + Interrupt Response
             + The PEC - Peripheral Event Controller
             + The Pipeline
             + Pipeline Side-Effects
             + Clock Speeds
             + The PLL
             + Bus Modes
                  + Memory Access Times
             + 80C166 Flavors
        o MICROCONTROLLER COMPARISONS
             + Context Switch Times
             + Comparison of CISC 196 vs RISC 166
        o SOURCES OF INFORMATION ON THE 80C166
             + Persons, email
             + FTP sites
             + Web pages
             + Mailing lists
             + BBSs
        o 80C166 PRODUCTS
             + Free languages and development tools
             + Commercially available products
        o 80C166 DOCUMENTATION

---------------------------------------------------------------------------

ABOUT THIS FAQ

This FAQ is available in HTML. The "home" is at the FAQ Library:

   * http://www.faqlib.com/80c166
     (Server located in California, USA)
   * http://www.ba-karlsruhe.de/faqlib/80c166
     (Server located in Germany)
   * http://www.vol.it/mirror/faqlib/80c166
     (Server located in Italy)

The plain ASCII version is stored in the above mentioned directories, using
the file name 80c166.txt. A zip file with the .html file and all the
diagrams is stored as 80c166.zip. A postscript version (not 100% up to
date) is available as 80c166.ps.

If you only have ftp access, use ftp://www.hitex.com/automation/faq.

Who put this FAQ together?

This FAQ is put together by Olaf 'Olu' Pfeiffer. Although I am working for
a company selling development tools for 80C166, I will try my best to keep
it unbiased. Surely this will NOT be "a sales pitch" - I am on the Internet
since 1988 and only received one flame (so far :-)

Special thanks to:

Michael Beach (Hitex UK) - Some of the technical parts are based on his
guide "An Introduction To The SAB80C166 Family". It is available in HTML:

   * http://www.ba-karlsruhe.de/automation/docs/166primer
   * http://www.hitex.com/automation/docs/166primer

Harald Lehmann (former Siemens US now Siemens Munich, Germany) - Thanks for
the support! This FAQ benefits from his input - e.g. the block diagramms.
Lot of info was taken from his BBS 1-800-366-0621.

Robert Boys (Hitex US, m68k FAQ, VMEbus FAQ, 68hc11 FAQ) - Thanks for lots
of valuable advice and for removing the Germanish from this FAQ 8^)

Russ Hersch (Israel, microcontroller primer FAQ, 8051 FAQ) - Thanks for a
good layout which I adopted for this FAQ.

How can I contribute to this FAQ?

That's easy. Just send your material to 80c166faq@hitex.com. If it is a
commercial entry, please prepare it for "cut & paste". Commercial entries
will NOT include long sales talk - just name your product and a contact
address. Email and Webpages preferred!

What newsgroups will this FAQ be posted to?

This FAQ will be posted once a month to the following newsgroups:

   * comp.arch.embedded
   * comp.realtime
   * comp.robotics.misc

May I distribute this FAQ or post it somewhere else?

Only if you leave the FAQ as it is! If you take the HTML version, make sure
you do not forget any file. Do NOT edit, add or delete any part of the FAQ.

How about FAQs on other microcontrollers?

Oh yeah! There are lot's of them. For a start, check out the FAQ Library:

   * http://www.faqlib.com
   * http://www.ba-karlsruhe.de/faqlib
   * http://www.vol.it/mirror/faqlib

---------------------------------------------------------------------------

ABOUT THE 80C166

The 80C166 is a 16-Bit microcontroller developed by Siemens. Second source
availablity by SGS-Thomson. Some performance indicators (as claimed by
Siemens):

   * 90% of instructions execute in 100ns at 20 MHz clock
   * 100ns context switching enhances task processing
   * Interrupt response 250ns min, 400ns typ. (50ns sample rate with
     C176/C165)
   * 500ns multiply, 1us divide
   * 10 channel 10-bit A/D converter, 9.7us sample time
   * Interrupts serviced by cycle stealing DMA (PEC)
   * 1024 point FFT calculated in 28ms
   * (Symmetrical, burst and single shot modes PWM)

The 80C166 Microcontroller - Overview

The 80C166 is a RISC CMOS 16-Bit microcontroller. The key features are:
(SABC167 Values)

   * 16 bit CPU with 4 stage pipeline and jump cache
   * 32 bit bus to internal 32K byte ROM
   * Flash 32K byte EEPROM version available [SAB 88C166-5S]
   * 1K (2K) bytes internal dual port RAM
   * 90% of instructions execute in 100ns at 20 MHz clock

   * Register based architecture with multiple variable banks
   * 100ns context switching enhances task processing
   * 8/16 bit external, mux/demux bus modes with HOLD/A
   * 2(5) simultaneous bus modes (each with a chip select)
   * Interrupt response 250ns min, 400ns typ. (50ns sample rate with
     C176/C165)

   * Interrupt with 16 priority levels in each of 4 groups
   * Interrupts serviced by cycle stealing DMA (PEC)
   * 10 (16) channel 10-bit A/D, 9.7us sample time
   * 500ns multiply, 1us divide
   * Watchdog - 16 bit programmable

   * 16 (32) capture/compare channels
   * based on two (four) 16-bit time bases
   * (4 channel PWM at 78KHz 8-bit resolution)
   * Boolean arithmetic and bit processing
   * 5 general purpose 16-bit timer/counters

   * von Neumann address space, 256K (16Mbytes)
   * 2 USART (SCC); 625KBaud async (5MBaud sync)
   * 76 (112) I/O lines
   * 100 (144) pin plastic metric quad flat pack (M-QFP) package

Registers, Context Pointer (CP)

Traditional microcontrollers have one or more special registers which can
be used for mathematical, logical or Boolean operations. In the 8051, there
is a single "accumulator" with 8 other registers which may be used for
handling local variables or intermediate results in complex calculations.
These additional registers are also used to access memory locations via
indirect and/or indexed addressing.

Conventional CPUs spend much time moving data from slow memory areas into
active registers. The RISC offers a very large number of general purpose
registers which may be used for local variables, parameters and
intermediates. The SAB80C166 provides sixteen 16-bit general purpose
registers (GPRs), each of which may function as an accumulator, indirect
pointer or index. With such a large number of GPR's available, it becomes
realistic to keep all local and intermediate variables within the CPU
throughout quite large procedures. This limits external memory accesses and
can yield a great increase in speed.

A GPR diagramm (gpr.gif, 15KB) is available from the HTML version of this
FAQ.

Further significant benefits are derived from the RISC technique of
register windowing. As stated above, up to 16 registers are available for
use by the program. However, by making the active register bank movable
within a larger on-chip RAM, the job of real time multi-tasking is
considerably eased.

Central to this is the concept of a "Context Pointer" (CP), which defines
the current absolute base address of the active bank. Thus a reference to
"R0" means the register at the address indicated by the CP. The 16
registers are then addressed with a 4-bit offset to the CP.

A good example of how the CP is used is with a background task and a
real-time interrupt existing at the same time. When the interrupt occurs,
rather than pushing all GPR's onto the stack, the CP of the current
register bank is stacked and simply switched to a new value, determined at
link time, to yield a fresh register bank. This results in a complete
context switch in just one machine cycle but does rule out the use of
recursion. A hybrid method, which permits re-entrancy, uses the stack
pointer to calculate the new CP dynamically. Here, on entering the
interrupt, the number of registers now required is subtracted from the
current SP and the result placed in CP, with the old CP stacked. Thus the
new register bank is located at the top of the old stack, with the old CP
and then the new stack following on immediately afterwards. On exiting the
interrupt routine, the original register bank is restored by POPping the
old CP from the stack. The SP is reinstated by adding the size of the new
register bank onto the current SP.

A further RISC refinement is register window overlapping which is when a
new procedure is called, part of the new register bank defined by CP' is
coincident with the original at CP:

        R3'  ; Register for subroutine's locals and intermediates
        R2'  ; Register for subroutine's locals and intermediates
    R7  R1'  ; Common register, R7 == R1'
CP' R6  R0'  ; Common register, R6 == R0'
    R5       ; Register for caller's locals and intermediates
    R4       ; Register for caller's locals and intermediates
    R3       ; Register for caller's locals and intermediates
    R2       ; Register for caller's locals and intermediates
    R1       ; Register for caller's locals and intermediates
CP  R0       ; Register for caller's locals and intermediates

;============================================================
MODULE 1
; *** Assignment Of GPRs To Local Variables - Caller ***

x_var   LIT     'R0'            ; Local variable
y_var   LIT     'R1'            ; Local variable

parm1   LIT     'R6'            ; Passed parameter 1
parm2   LIT     'R7'            ; Passed parameter 2

result  LIT     'R6'            ; Value returned from sub routine

;============================================================
MODULE 2
; *** Assignment Of GPRs To Local Variables - Sub Routine ***

a_var   LIT     'R2'            ; Local variable
b_var   LIT     'R3'            ; Local variable

input1  LIT     'R0'            ; Received parameter 1
input2  LIT     'R1'            ; Received parameter 2
ret1    LIT     'R0'            ; Final result returned in R0

By using some forethought, the programmer should arrange for any value to
be passed to the subroutine to be located in the common area so that all
the normal loading and unloading of parameters is avoided. This technique
can be used in either absolute or SP-relative register bank modes.

To get the best from a RISC's registers, the location of data needs careful
consideration: although highly orthogonal, the limited number of addressing
modes provided for MUL and DIV for example, can appear somewhat
restrictive. Fortunately though, most operands involved will already be in
registers, so eliminating the need for many addressing techniques.

Address Space

The 80C166 family has an segmented address space of up to 16MB (256KB on
the 80C166). Code segments are of 64KB size, data pages of 16KB size.
Additionally, 64KB non segmented address space is available.

The internal address space is up to 128KB ROM/Flash-EPROM (32KB on the
80C166). Depending on the derivative, there are up to 4KB RAM and 1KB SFR's
present.

With the HTML version of this FAQ two disgramms on the address space are
available:

  1. The Memory Map (memmap.gif, 15KB) shows the internal and external
     address space for all derivatives.
  2. The Adressing Scheme (dppxaddr.gif, 13KB) shows how the code segments
     and data pages are addressed. This is done using the Code Segment
     Pointer (CSP) and the 4 Data Page Pointers (DPPx).

Interrupt Response

In the SAB80C166, branches to interrupts make use of the injected
instruction technique and thus vectoring to service routines are achieved
in only min 250ns (400ns typ.). The effect of complex but necessary
instructions such as MUL and DIV (5 and 10 cycles respectively) might be
expected to stretch this, but it is interesting to note that the SAB80C166
provides these as interruptable instructions.

Very fast interrupt service is crucial in high-end applications such as
engine management systems, servo drives and radar systems where real-world
timings are used in DSP-style calculations. As these normally form part of
a larger closed control loop, erratic latency times manifest themselves as
undesirable jitters in the controlled variable.

The PEC - Peripheral Event Controller

PEC stands for Peripheral Event Controller. The PEC offers the fastest
response times to interrupt requests. Depending on the priority level and
used bus mode the response time can be as fast as 250ns! Triggered by
interrupts, the PEC can perform a single Byte or Word transfer between two
locations. A PEC transfer holds the running program for just 1 instruction
cycle. No data needs to be saved tp process a PEC transfer.

The 8 PEC channels each have their own control register, source and
destination pointer and can operate independantly. One - and only one - of
the two pointers (source OR destination) can be automatically incremented
on each PEC transfer. Reading and writing to a serial port implemented by
using PEC channels uses a minimum of CPU time, even at highest speeds.

The Pipeline

To maximise the rate at which instructions are executed, RISC CPU's are
very heavily pipelined. On any given machine cycle, the 80C166 can process
up to 4 instructions simultaneously by overlapping the various steps:

FETCH:
     get the opcode from the program store
DECODE:
     identify the opcode from a small list and fetch operands
EXECUTE:
     perform the operation denoted by opcode and initiate write result
WRITE-BACK:
     result is returned to the specified location

Although the instruction takes four machine cycles, it is apparently
executed in just one (2 state times). Pipelining has considerable benefits
for speeding up sequential code execution as the bus is guaranteed to be
more fully utilised.

Pipeline Side-Effects

However, the fetch and decode phases can simultaneously request access to
the bus, if for example, the final phase of the current instruction is a
READ. The External Bus Controller applies a WRITE, FETCH, READ priority to
prevent bus conflicts.

Coping with MUL and DIV

Multiply and divide instructions require 5 and 10 cycles respectively and
constitute the only "complex" opcodes within the RISC. These instructions
do not finish in the mandatory four (one bus) cycles. As it is not
practicable to stop the pipeline during longer instructions, dummy
instructions are injected into the decode stage, passing through the
remaining stages as simple NOP instructions.

Branches

While in-line code poses no problems for a pipelined CPU, branches require
special steps. The problem is that by the time the branch instruction has
reached the EXECUTE stage, the next in-line opcode has already been
FETCHED. Thus the instruction immediately after the branch will be
executed, followed by a jump to the target address for the branch. This
peculiarity is termed a "delayed branch" and is used as an alternative to
flushing out the pipeline completely.

The situation with a conditional branch is more complicated as the next
instruction may be totally inappropriate given the result of the
conditional test. The only solution is to either add a NOP or flush the
pipeline.

The solution taken in the SAB80C166 is to, in the first case, inject a
dummy instruction into the DECODE stage while the real target address is
being FETCHED. Thus, a single extra machine cycle is required to execute
the branch. For the conditional branch, the dummy is only injected if the
branch is made, and not for no-branch situations, saving time.

Loop Control

A common situation in embedded control is searching through a table. This
involves repetitive branching to a single fixed address. Without taking
special steps, a wasted machine cycle would occur during each loop. Bearing
some relationship to disk caching techniques on PC's, a "jump cache" is
provided. On the first time through the loop, the dummy instruction is
injected as before and a single machine cycle is wasted. However, the
branch target address is simultaneously stored in a cache area. Now, on
subsequent passes through the loop, the target address is extracted from
the cache and injected directly into the DECODE stage. The branch now
occurs in a single machine cycle.

Coding Around The Pipeline

With the parallel nature of the CPU, care has to taken to avoid pipeline
"mirages". Most potential problems originate from the WRITE-BACK stage
using addresses that have been changed by subsequently FETCHED
instructions. Although special hardware is provided for artificially
bringing forward operand READs and WRITEs, some pipeline effects must still
be kept in mind.

As an example, the general purpose register R0 is to be loaded with a value
at the top of the stack, after the stack pointer "SP" has been moved to a
new address of 0FA40H:

SP = 0FA80H
0FA80H = 0FFH   - Value at old top of stack

SP = 0FA40H
0FA40H = 011H   - Value at new top of stack

MOV SP,#0FA40H  ; Set stack pointer to new location
POP R0          ; Get value at top of stack into R0

           Machine Cycle Number ->>
-----------------------------------------------------------------------------
           0              1           2              3           4

FETCH      SP=0FA80H      R0=XX
           Get            Get POP R0
           MOV SP,#0FA40

DECODE                    SP=0FA80     R0=XX
(and get                  Get address  Get address
operands)                 of SP        of R0 & value
                                       in SP (still
                                       at 0FA80H)

EXECUTE                                SP=0FA80      R0=XX

WRITE-BACK                                           R0=0FFH     R0 POPped
                                                     Put #0FA40  from address
                                                     into SP     #0FA80H

---------------------------------------------------------------------------
As the instructions overlap, the value POPed into R0 will be incorrect. By
putting an instruction between the MOV and POP, the value of SP will be
already at the new value by the time the POP gets the value of SP. Note
that as WRITE overrules READ, the updating of SP will occur before the
READing of the SP value in the decode stage of POP R0. The overlapping of
instructions produces a similar effect when disabling interrupts:

1   BCLR IEN
2   <start of region which may not be interrupted>
3   .
4   .
5   .

As the actual updating of the IEN register does not occur until machine
cycle 3, either NOPs must be inserted in cycles 2 & 3 before the critical
region or the interrupt disable command must be moved back two
instructions.

Clock Speeds

The SAB80C166 has a divide by two prescaler so that a 40MHz XTAL or
oscillator is required to yield the maximum possible 20MHz CPU clock. The
basic unit of time in the C166 core is a single state time, corresponding
to 50ns at 20MHz. Most SAB80C166 instructions execute in two state times,
i.e. 100ns.

The 'W'-suffixed parts have no divide by two and thus can use a 20MHz clock
source directly. Note that these parts must be used with a crystal as they
must have a 50% duty cycle clock, which cannot be guaranteed with an
oscillator module.

If an oscillator module is used, it must have a rise and fall time of <5ns.
As with other high clock rate CPUs (80C186XL-16 etc.), 40 and 32MHz
crystals must be of the parallel resonance type. These can be tricky to
find and so a cheap series resonant crystal used with an 74HC04 inverter
could be an alternative to a full oscillator module.

The C167CR and C167SR are all of the 'W' type in that they can use a 20MHz
crystal. They can also use a 5Mhz crystal and use the on-chip PLL to
perform a x4 frequency multiplication up to the usual 20MHz.

Siemens' recommended oscillator circuit for the 40 MHz version:

          C2       R2 ____                    C2 = 27pF +/- 20%
       +--||---+-----|____|---O XTAL 2        R2 = 0..500 Ohm
       |       |
  GND--|     |XXX| Crystal (3rd Overtone)
       |  C1   |
       +--||---+--------------O XTAL 1        C1 = 39pF +/- 20%
               |
              |X|
              |X| L1 = 1.5 uH +/- 20%
              |X|
             __|__
             _____ C3 = 1nF
               |
              GND

Note: This will work in 80% of all applications. Every design is specific
(noise, layout). An oscillator circuit research/development might be
necessary for user specific circuits.

The PLL

Some of the derivatives have an on-chip PLL Oscilator. PLL stands for Phase
Locked Loop and it allows to operate the microcontroller on a low frequency
external clock. Using the PLL the external clock is internally multiplied
by 4. So an internal clock of 20 Mhz can be obtained using an external 5
Mhz clock.

The PLL is activated via a high signal on pin PH0.7 during reset. As long
as an external clock is provided, the PLL constantly synchronizes itself to
it. Interrupt requests are generated when frequency changes are detected.
Even on a total loss of the clock, the CPU can still execute emergency
actions as the PLL's basic frequency of 2...10Mhz will even be provided if
NO external clock is available.

Bus Modes

The 80C166 has five bus modes:

   * Single Chip Mode
   * 16/18-Bit Address, 8-Bit Data, Multiplexed Bus
   * 16/18-Bit Address, 8-Bit Data, Non-Multiplexed Bus
   * 16/18-Bit Address, 16-Bit Data, Multiplexed Bus
   * 16/18-Bit Address, 16-Bit Data, Non-Multiplexed Bus

The basic philosophy behind the bus interface is simplicity: by providing
non-multiplexed modes, it is possible to provide just a ROM and RAM to make
a working SAB80C166 system. Derivatives with integrated chip selects can
make all decoder logic redundant. Thus, despite is 20 fold improvement in
performance, a C166 digital design can be simpler than an 8031!

One of the SAB80C166's most useful features is its ability to support two
different bus configurations in a single hardware design. Thus while the
main code and data areas can be 16 bit non-multiplexed with zero wait
states for best speed, slow (and low cost) peripherals such as RTCs can be
addressed with, for example, and 8-bit bus with 3 wait states.

This secondary bus mode is controlled by the BUSCON1 and ADDRESEL1
registers which set the mode and address range base address respectively.
In the C165 and C167, a further 3 secondary bus regions can be defined,
each with its own external chip select (CS) pin for direct connection to
peripheral devices' chip enable inputs.

Memory Access Times

In the following table, times are given for 20 MHz (40 MHz internal) CPU
clock rate. Please note: the external bus speed is optimised by prefetching
into the instruction queue!

                         16 bit Data  16 bit Data  8 bit Data  8 bit Data
                 Single   16/24 bit    16/24 bit   16/24 bit    16/24 bit
               Chip Mode     Addr        Addr         Addr        Addr
                           NON MUX        MUX       NON MUX        MUX
   Used Ports     none    Port 0,1,4   Port 1,4    Port 0,1,4   Port 1,4
 Address Latch    none       none       16 bit        none        8 bit
   Bus Cycle     100ns/     100ns/      150ns/       100ns/      150ns/
    Time at      100ns/     150ns/      200ns/       150ns/      200ns/
    0/1/2 WS     100ns      200ns        250ns       200ns        250ns
  Instr. Fetch   100ns/     100ns/      150ns/       200ns/      300ns/
  Time 1 Word    100ns/     150ns/      200ns/       300ns/      400ns/
  at 0/1/2 WS    100ns      200ns        250ns       400ns        500ns
  Instr Fetch    100ns/     200ns/      200ns/       400ns/      600ns/
  Time 2 Word    100ns/     300ns/      300ns/       600ns/      800ns/
  at 0/1/2 WS    100ns      400ns        400ns       800ns         1us
     EPROM                  70ns/        70ns/       70ns/        70ns/
  Access Time     n.a.      120ns/      120ns/       120ns/      120ns/
  at 0/1/2 WS               170ns        170ns       170ns        170ns
    Relative       1/        1.2/        1.5/         2.0/        3.0/
     Speed         1/        1.5/        2.0/         2.5/        4.5/
  at 0/1/2 WS      1         2.0          2.5         3.0          6.0

(WS = Wait States)

80C166 Flavors

Technology: CMOS

Ambient Temp: 0*C to +70 *C, -40*C to +125 *C

VCC: 5 volts +- 10%

Power: 90-180 mA,

Idle/Powerdown: 20 mA, 100 *A

   * SAB80C166-M: 20 MHz, 1K RAM, ROMless, P-MQFP 100-2
   * SAB83C166-5M: 20 MHz, 1K RAM, 32K ROM, P-MQFP 100-2
   * SAB88C166-5M: 20 MHz, 1K RAM, 32K FLASH, P-MQFP 100-2
     ST10F166BQ1: Same as above, second source by SGS-THOMSON
   * SABC167S-4RM: 20 MHz, 2K RAM, 32K ROM, P-MQFP 144-1
   * SABC167SR-LM: 20 MHz/PLL, 4K RAM, ROMless, P-MQFP 144-1
   * SABC167CR-LM: 20 MHz/PLL, 4K RAM, ROMless, CAN, P-MQFP 144-1
   * SABC165-LM: 20 MHz, 2K RAM, ROMless, P-MQFP 100-2
     ST10R165BQ1: Same as above, second source by SGS-THOMSON
   * SABC165-LF: 20 MHz, 2K RAM, ROMless, T-MQFP
     ST10R165BT1: Same as above, second source by SGS-THOMSON
   * SABC165-L25F: 25 MHz, 2K RAM, ROMless, T-MQFP

Block Diagramms

The following block diagramms are available with the HTML version of this
FAQ:

   * CPU Core (coreblk.gif, 15KB)
   * 80C166 (c166blk.gif, 20KB)
   * C167 (c167blk.gif, 23KB)
   * C165 (c165blk.gif, 19KB)
   * C163 (c163blk.gif, 19KB)

---------------------------------------------------------------------------

MICROCONTROLLER COMPARISONS

Comparing microcontrollers is always difficult. Usually each chip
manufacturer has benchmarks showing that their controller is the best. The
following comparisons were published by third party support companies,
which all offer products for microcontrollers from several manufacturers...

Context Switch Times

CMX published a white paper about the context switch times of their
CMX-REAL-Time Multi-Tasking Operating System on different microcontrollers.
Before reading the results, you should take yourself the time to read the
following notes:

  1. The "Context Switch Time" was calculated on the current task that was
     running, having its context saved and the higher priority users' task
     becoming the new running task.
  2. The scheduler is written in assembly. So the context switch times
     stated are not dependant on any compiler.
  3. CMX tried to use "comparable" memory models on each microcontroller.
     Paging was not used. No wait states were introduced.
  4. The 80C166 has 2 stack areas (SYSTEM and USER). The RTOS saves and
     restores the SYSTEM stack during saving or restoring of a task. The
     SYSTEM stack is only used to store the return addresses of nested
     functions called by a task. Depending on the number of words used by
     the system stack, the context switch time may increase. Add 500
     nanoseconds for each word in the stack.

And now - let's see the result:

 MicrocontrollerInternal Speed Context Switch Time Speed Factor
     80C166     20 MHz         11.20 microseconds       1
      68332     20 MHz         25.15 microseconds      1.13
     68HC16     16.78 MHz      41.50 microseconds      1.55
      80196     20 MHz         37.80 microseconds      1.69

The Speed Factor is a theoretic value: if all processors would run with the
same internal speed, they would need "Speed Factor" times longer for the
context switching (compared to the 80C166 - "of course").

Comparison of CISC 196 vs RISC 166

The following is a comparison of the machine cycles needed to finish
instructions on a CISC and on a RISC architecture.

                         CISC             RISC
--------------------------------------------------------------------------
Number of
Basic Instructions       85               55

Instruction              80C196  Cycles   80C166       Cycles    Difference
--------------------------------------------------------------------------
Move word direct         LD x,y       4   MOV Rw,Rw         2    2
Move word indirect       LD x,[y]     5   MOV Rw,[Rw]       2    3
Move word indexed        LD x,z[y]    7   MOV Rw,[Rw+#d16]  4    3

Add words direct         ADD x,y      4   ADD Rw,Rw         2    2
Add words indirect       ADD x,[y]    5   ADD Rw,[Rw]       2    3
Add words indexed        ADD x,x[y]   7   ADD Rw,[RW+#d16]  4    3

Multiply words direct    MUL x,y     16   MUL Rw,Rw        10    6
Multiply words indirect  MUL x,[y]   18   N/A
Multiply words indexed   MUL x,x[y]  20   N/A

Divide words direct      DIV x,y     26   DIV Rw           20    6
Divide words indirect    DIV x,[y]   28   N/A
Divide words indexed     DIV x,z[y]  30   N/A

16 bit uncond.jump       LJMP #16     7   JMPA cc_UC,#d16   4    3
Shift Left 16 places     SHL x,#16   22   SHL Rw,Rw         4(*) 18
Software interrupt       TRAP        16   TRAP #n           4    12
Return from subroutine   RET         11   RET               2    9

Direct data on stack     PUSH x       6   PUSH Rw           2    4
Indirect data on stack   PUSH [y]     9   N/A
Indexed data on stack    PUSH z[y]   10   N/A
--------------------------------------------------------------------------

(*) with SAB80C166, both operands in shift must be held in registers and
hence an additional two states area included for loading number of shifts
into a GPR, Rw.

By considering the simpler instructions which form the bulk of any program,
it can be seen that the CISC requires approximately twice the number of
state times of the RISC. For instructions that change program flow, the
CISC overhead is even greater at a factor of 4. Taken over a complete
software system, the RISC advantage should be a reduction in run times by
about 50%.

---------------------------------------------------------------------------

SOURCES OF INFORMATION ON THE 80C166

Here I really rely on YOUR help. If YOU know anything to add here, please
send me an email: 80c166faq@Hitex.com

Persons, email

If you have a question concerning the 80C166 / ST10 which are NOT answered
by this FAQ, you may want to send it to one of the following email
addresses:

   * Hitex: 166team@hitex.com
   * Keil USA: c166@keil.com
   * Siemens Europe/Germany: Harald.Lehmann@p54.mch2.siemens.net
   * Siemens USA: microlab@siecomp.com
   * SGS-Thomson: thierry.cravoisier@st.com

FTP sites

Public domain cross assembler AS (documentation in German):
ftp://ftp.uni-stuttgart.de/pub/systems/pc/programming/as

Web pages

   * Siemens Home Page: http://www.sci.siemens.com
   * SGS-Thomson Home Page: http://www.st.com
   * 166Primer: http://www.hitex.com/automation/docs/166primer
   * Commercial web pages (third party support) are listed below in
     paragraph "Commercially available products"

Mailing lists

I know of none so far - please let me know if you do!

BBSs

Siemens Components, Inc. BBS of the Integrated Circuit Division
     Cupertino, California 1-800-366-0621 or (408) 777-4916

     Lots of application notes, example programs and errata sheets.
Siemens
     Muenchen, Germany (+49) 89/ 49 84 31

     Even more info...

80C166 PRODUCTS

This list will grow - check it out regularly...

Free languages and development tools

The only free tool I know so far, is a 166 simulator:
http://www.hitex.com/hitex/demo

Free Assembler

Public domain cross assembler AS (documentation in German):
ftp://ftp.uni-stuttgart.de/pub/systems/pc/lang/as

Free C compilers

I know of none so far - please let me know

Commercially available products

Please note: all company entries are alphabetically ordered. Companies
offering web pages or at least having an email address are preferred. Other
sources for this kind of information are Siemens' Bulletin Board Systems
and Siemens' Web pages http://www.sci.siemens.com.

   * Simulator
        o Hitex Development Tools http://www.hitex.com, San Jose, CA,
          800-45-HITEX
        o Keil Software http://www.keil.com, Dallas, TX, 800-348-8051
        o Tasking http://www.tasking.com, Dedham, MA, 800-458-8276
   * Evaluation Board & Debugger
        o Hitex Development Tools http://www.hitex.com, San Jose, CA,
          800-45-HITEX
        o Rigel Corporation http://www.rigelcorp.com, Gainesville, FL (904)
          373-4629
        o Phytec http://www.phytec.de, Bainbridge, WA, (206) 780-9047
        o Siemens (USA) http://www.sci.siemens.com
   * Emulator
        o Hitex Development Tools http://www.hitex.com, San Jose, CA,
          800-454-4839
          To keep this FAQ unbiased I should mention that Hitex is not the
          only manufacturer of In-Circuit Emulators for the 80C166 ;-)
        o Kontron http://www.kontron.com
        o Lauterbach http://www.lauterbach.com
   * Assembler, Compiler, Linker, Loader
        o Keil Software http://www.keil.com, Dallas, TX, 800-348-8051
        o Tasking http://www.tasking.com, Dedham, MA, 800-458-8276
        o HighTec (GNU compiler, available at:
          http://www.hitex.com/hitex/demo), Saarbruecken, Germany, +49 681
          926130
        o AM Research, Forth development environement,
          http://www.amresearch.com
   * Real Time Operation Systems
        o CMX, CMX Company, http://www.cmx.com, Framingham, MA, (508)
          872-7675
        o ENEA DATA AB, OSE, http://www.enea.se , Sweden, +46 8 638 50 00
        o PXROS, http://www.hitex.com/hitex/demo, HighTec, Saarbruecken,
          Germany, +49 681 926130
        o RTXC, Embedded Systems Products, Houston, TX, 800-525-4302
        o RTX166, Keil Software http://www.keil.com, Dallas, TX,
          800-348-8051
        o VxWorks, WindRiver Systems, Alameda, CA, (510) 748-4100
   * Misc
        o USNET, a TCP/IP networking suite for 80C166, US Software, (503)
          641-8446, ussw@netcom.com

80C166 DOCUMENTATION

The 166 Primer and an introduction to CAN (Controller Area Network) are
here:

   * http://www.ba-karlsruhe.de/automation/docs
   * http://www.hitex.com/automation/docs

The SABC167CR-LM has a build in CAN interface.

SGS-Thomson offers their manuals in .PDF files. The following books are
available from their web page
http://www.st.com/stonline/books/pdf/menu/03010113.htm:

   * C167 FAMILY PRELIMINARY USER MANUAL (ST10 FAMILY)
   * ST10 FAMILY 16-BIT MCU PROGRAMMING MANUAL
   * ST10166 16-BIT MCU USER MANUAL
   * ST10F160/166 - 16-BIT MCU WITH 256K FLASH MEMORY
   * ST10R165 - 16-BIT ROMLESS MICROCONTROLLER
   * ST10R165UM - ST10R165 16-BIT MCU USER MANUAL

---------------------------------------------------------------------------

And now - to something completely different: the disclaimer:

Copied from Russ Hersch - as I don't think that I could have said it
better...

I disclaim everything. The contents of this article might be totally
inaccurate, inappropriate, misguided, or otherwise perverse - except for my
name (hopefully I got that right).

Copyright (c) 1995, 1996 by Olaf 'Olu' Pfeiffer, all rights reserved. This
FAQ may be posted to any USENET newsgroup, on-line service, or BBS as long
as it is posted in its entirety and includes this copyright statement.

This FAQ may not be distributed for financial gain.

This FAQ may not be included in commercial collections or compilations
without express permission from the author.

---THATS-THE-END-OF-THIS-FAQ-(for-now)---------------------------------------
