
*************** Control logic generation ************
genlib -v control

scr -p -r -a 2 instruction_decoder

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************** RAM generation **************
rage 16 256 -m -u -layout -vhdl -datasheet -o sram_a

rage 16 256 -m -u -layout -vhdl -datasheet -o sram_b

genlib -v ram

bbr sram -v -o sram vdd 12 vss 12

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************** Data Path Generation **************
rsa 16 -cin -cout -overn -virtual -layout -vhdl -datasheet -o addsub

fpgen -v dpath

dpr -V -p -r data_path data_path


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************** Control+Data_Path generation **************
genlib -v core

bbr core -v -o core vdd 12 vss 12

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The following does not work.
************** RAM+core generation **************
genlib -v ram+core

bbr ram+core -v -o core+dp vdd 12 vss 12

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