Custom libraries

Two full-custom parameterized generators are also available. They produce stand-alone blocks, that are to be routed only at the floorplan level with other blocks, using either bbr or better xcheops.

• ROM and RAM generators:

  grog ,

  a generic ROM generator. The interface is an address bus, a clock and an output enable signal, and a data out bus. The coding format to specify the ROM contents is a limited subset of VHDL. 
  

  Params	Meaning	Range
  nb	number of bits	1 to 64
  nw	number of words	64, 128, 256, n 512, 1 $\leq$ n $\leq$ 8
  hz	tri-state output	true or false

  rage ,

  a RAM generator. The interface has a read/write address, a write signal indicating if a read or a write is to be performed, and a clock. 
  

  Params	Meaning	Range
  nb	number of bits	2 to 128
  nw	number of words	128 to 4096
  aspect	aspect ratio	narrow, medium or large
  ud	unidirectional, ie share the same bus for data in and out	true or false

All these generators have been designed using the Alliance CAD tools, for both design and verification phases.

 

Alliance Web Site © 1997, 2002 ASIM/LIP6/UPMC, page maintained by Czo [Olivier Sirol] , last updated on 26 May 2000.