# For now we keep a common commands file for verilog
# and vhdl modes. We should implement control constructs
# to load language specific commands.
alias ls csh ls -C
alias cv csh cv
alias run_options runoptions
alias select_design synthesize
alias report_cost set_cost
alias quit exit
alias input_load input_maxload
alias set_behav_mod_gen skill snAddVsynOption("+behav_mod_gen")
alias unset_behav_mod_gen skill snRemVsynOption("+behav_mod_gen")
alias model_cell model_cells
#
# Ensure that . is in the search path to begin with
add_path /users/outil3/cadal/hdl_synthesis /users/outil3/cadal
#
# Language specific initializations.
#
skill _snRun->runoptions->RR = t
#
# Tool Specific initialization
#
# Enable Test Synthesis
skill if( getd('snHiSetFieldSensitive) snHiSetFieldSensitive("runSynthesizerForm" "snRunOptionsTest" t) )
library -target ScLib_synth
library -source ScLib_synth
library -symbol ScLib basic
synthesis_options -jobpriority 20
synthesis_options -steps schematic 
