simVerilogNetlistFileList = '(
    (("DEMO_ALU" "circuit") 
	("cds4/netlist" "cds4/map" "schematic")
    ) 
    (("DEMO_ALU" "mux4") 
	("cds3/netlist" "cds3/map" "schematic")
    ) 
    (("DEMO_ALU" "adder_4bits") 
	("cds2/netlist" "cds2/map" "schematic")
    ) 
    (("DEMO_ALU" "F_adder") 
	("cds1/netlist" "cds1/map" "schematic")
    ) 
    (("DEMO_ALU" "accu_4bits") 
	("cds0/netlist" "cds0/map" "schematic")
    )
)
simVerilogNetlistFileLibList = '("DEMO_ALU")
simVerilogNetlistFileCellList = '(("DEMO_ALU" 
	("accu_4bits" "F_adder" "adder_4bits" "mux4" "circuit")
    )
)
hnlIncrementalDirectory = '"ihnl"
