;Setup Menu Forms
;Setup Environment
;Run Directory
vlogifVicSimRunDir = "/users/outil3/cadal/DesignKit_CADAL/demo_date99/circuit.run2"

;Library
vlogifVicSimLibName = "DEMO_ALU"

;Cell
vlogifVicSimCellName = "circuit"

;View
vlogifVicSimViewName = "schematic"

;Run Simulation
vlogifSimRunMode = "locally"

;On Host
simHost = "localhost"

;Remote Simulation Host Name
vlogifSimRemoteHostName = 'nil

;by
vlogifSimRemoteMode = "mounting"

;Run Directory As Viewed By Simulation Host
vlogifSimRemMountDir = ""

;Directory On Simulation Host To Temporarily Store Run Directory
vlogifSimRemCopyDir = ""

;Use Delay Annotation File At Time Zero
vlogifUseSDF = 'nil

;Verilog Netlisting Options
;Netlist Entire Design
simReNetlistAll = t

;Netlist For LAI/LMSI Models
simVerilogLaiLmsiNetlisting = 'nil

;Netlist These Views
verilogSimViewList = '("behavioral" "functional" "system" "verilog" "pld_verilog"
    "lai_verilog" "lmsi_verilog" "schematic" "symbol"
)

;Netlist Automatically to Simulate Design Changes
simVerilogAutoNetlisting = t

;Use TestFixture
simVerilogTestFixtureFlag = t

;Generate Test Fixture Template
simVerilogTestFixtureTemplate = "All"

;Netlist Explicitly
simVerilogNetlistExplicit = 'nil

;Preserve Buses
simVerilogFlattenBuses = t

;Netlist Uppercase
vtoolsUseUpperCaseFlag = 'nil

;Generate Pin Map
hnlVerilogCreatePM = 'nil

;Netlist SwitchRC
simVerilogHandleSwitchRCData = 'nil

;Skip Null Port
simVerilogProcessNullPorts = 'nil

;Netlist Uselib
simVerilogHandleUseLib = 'nil

;Drop Port Range
simVerilogDropPortRange = t

;Incremental Config List
simVerilogIncrementalNetlistConfigList = 'nil

;Symbol Implicit
hnlVerilogNetlistStopCellImplicit = 'nil

;Global TimeScale Overwrite Schematic TimeScale
simVerilogOverWriteSchTimeScale = 'nil

;Declare Global Locally
vlogifDeclareGlobalNetLocal = 'nil

;Skip Timing Information
vlogifSkipTimingInfo = 'nil

;Assign For Alias
vlogifUseAssignsForAlias = 'nil

;Support Escape Names
simVerilogEnableEscapeNameMapping = 'nil

;Stop Netlisting at Views 
verilogSimStopList = '("verilog" "pld_verilog" "lai_verilog" "lmsi_verilog" "symbol")

;Global Power Nets
simVerilogPwrNetList = '("vdd!" "VDD!" "PWR!" "VCC!")

;Global Ground Nets
simVerilogGndNetList = '("gnd!" "GND!")

;Global Sim Time
simVerilogSimTimeValue = 1

;Unit
simVerilogSimTimeUnit = "ns"

;Global Sim Precision
simVerilogSimPrecisionValue = 1

;Unit
simVerilogSimPrecisionUnit = "ns"

;Force ReNetlist Reasons
vtoolsifForceReNetlisting = 'nil

;Simulation Options
;Command File
simVerilogInteractiveCommandFile = ""

;Options File
simVerilogInvocationOptionsFile = ""

;Other Options
simVerilogInvocationOptions = "/users/outil3/cadal/DesignKit_CADAL//verilog/techno +libext+.v "

;Library Files
simVerilogLibraryFile = ""

;Library Directories
simVerilogLibraryDirectory = "/users/outil3/cadal/DesignKit_CADAL//verilog_99"

;Verilog-XL Executable
verilogSimBinary = "/users/soft2/opus/Mars99/tools/bin/verilog"

;Simulation Log File
verilogLogFile = "simout.tmp"

;Stop After Compilation
simVerilogStopAfterCompilation = t

;Record Signals Options
;Waveform Display Package
simVerilogWavePackageVar = "SimWave"

;in Simulation History File
simVerilogResultsShmFile = "shm.db"

;Save
simVerilogShmInvokeChoice = "Top Level Primary I/O"

;Save Shm Results
simVerilogShmResultInvokeBoolean = t

;Run SHM
vlogifShmRunMode = "locally"

;On Host
vlogifShmHostName = "localhost"

;Remote Shmd Host Name
vlogifShmRemoteHostName = 'nil

;by
vlogifShmRemoteMode = "mounting"

;Run Directory As Viewed By SHM Host
vlogifShmRemMountDir = "/users/outil3/cadal/alu_1bit.run1"

;Directory On SHM Host To Temporarily Store Run Directory
vlogifShmRemCopyDir = ""

; Stimulus file list
;Test Fixture files
vlogifTestFixtureFileList = '("testfixture.verilog")

;Current test fixture
vlogifCurrentTestFixture = "/users/outil3/cadal/DesignKit_CADAL/demo_date99/circuit.run2/testfixture.verilog"

;Full Test files 
vlogifFullTestFileList = '(" ")

;Self Stimulus Reference Name
vicSelfStimulusHandle = "SelfStimulus"

;Test Fixture RunObject List
vlogifTFRunObjectList = '(
    (nil checkSyntax nil dip "test.top"
    currentShmDb nil dbList 
    ("shm.db") fileType
    "Stimulus" runObject "RunObject.0" testfixture "testfixture.verilog"
    )
)

;Design Instance Path
simVerilogTopLevelModuleName = "test.top"

;VCompare Executable
vlogifVCompareExecutable = "/users/soft2/opus/tools/bin/simcompare"

;Remote Simulation Netlisting Check
vlogifRemoteSimNetlistCheck = t

;Simulation Run Time Options
vlogifSetupOptionsDPL = '(nil vicSetupResultsMemoryUnit "ns" vicSetupResultsMemoryValue 0.0
vicSetupResultsMemoryMode "Unlimited" vicSetupResultsShmFile "shm.db" vicSetupResultsInvokeShmChoice
"Top Level Primary I/O" vicSetupResultsInvokeShmBoolean t vicSetupSimLogBoolean t
vicSetupSimUseHierarchyBrowser t vicSetupSimSuppressWarning nil vicSetupSimSuppressMessage
nil vicSetupSimPulseCtlSpecparam nil vicSetupSimPulseCtlReject 100
vicSetupSimPulseCtlError 100 vicSetupSimDelayTypeRadio "Typical" vicSetupSimDelayModeRadio
"Path" vicSetupSimBehaviorProfiler nil vicSetupSimTurboRadio "Default"
vicSetupSimTwinTurbo nil vicSetupSimSxlRadio "Minimum" vicSetupSimSwitch
nil vicSetupSimContAssign nil vicSetupSimNormal t
vicSetupEnvSDFScaleMax 1.0 vicSetupEnvSDFScaleTyp 1.0 vicSetupEnvSDFScaleMin
1.0 vicSetupEnvSDFScaleFactorConfig nil vicSetupEnvSDFScaleType "Min_Typ_Max"
vicSetupEnvSDFDelayType "Tool Control" vicSetupEnvSDFLogFile "sdf.log" vicSetupEnvSDFConfigFile
"" vicSetupEnvSDFModuleInst "" vicSetupEnvSDFScope ""
vicSetupEnvSdf2SdfOutputFileName "" vicSetupEnvSDFFileName "" vicSetupEnvSuppressSdf2Sdf
nil
)

