// Library - DEMO_ALU, Cell - adder_4bits, View - schematic
// LAST TIME SAVED: Mar  4 21:11:00 1999
// NETLIST TIME: Mar  5 18:25:03 1999
`timescale 1ns / 1ns 

module adder_4bits ( cout, s_0_, s_1_, s_2_, s_3_, a_0_, a_1_, a_2_,
     a_3_, b_0_, b_1_, b_2_, b_3_, cin );
output  cout, s_0_, s_1_, s_2_, s_3_;


input  a_0_, a_1_, a_2_, a_3_, b_0_, b_1_, b_2_, b_3_, cin;





specify 
    specparam CDS_LIBNAME  = "DEMO_ALU";
    specparam CDS_CELLNAME = "adder_4bits";
    specparam CDS_VIEWNAME = "schematic";
endspecify

F_adder I3 ( cout, s_3_, a_3_, b_3_, net21);
F_adder I2 ( net21, s_2_, a_2_, b_2_, net26);
F_adder I1 ( net26, s_1_, a_1_, b_1_, net31);
F_adder I0 ( net31, s_0_, a_0_, b_0_, cin);

endmodule
