// Library - DEMO_ALU, Cell - mux4, View - schematic
// LAST TIME SAVED: Mar  4 21:22:47 1999
// NETLIST TIME: Mar  5 18:25:03 1999
`timescale 1ns / 1ns 

module mux4 ( s_0_, s_1_, s_2_, s_3_, a_0_, a_1_, a_2_, a_3_, b_0_,
     b_1_, b_2_, b_3_, sel );
output  s_0_, s_1_, s_2_, s_3_;


input  a_0_, a_1_, a_2_, a_3_, b_0_, b_1_, b_2_, b_3_, sel;





specify 
    specparam CDS_LIBNAME  = "DEMO_ALU";
    specparam CDS_CELLNAME = "mux4";
    specparam CDS_VIEWNAME = "schematic";
endspecify

n1_y  I20 ( .i(sel), .f(net60));
mx2_y  I17 ( .l1(sel), .t(s_1_), .i1(b_1_), .l0(net60), .i0(a_1_));
mx2_y  I19 ( .l1(sel), .t(s_3_), .i1(b_3_), .l0(net60), .i0(a_3_));
mx2_y  I18 ( .l1(sel), .t(s_2_), .i1(b_2_), .l0(net60), .i0(a_2_));
mx2_y  I0 ( .l1(sel), .l0(net60), .i0(a_0_), .t(s_0_), .i1(b_0_));

endmodule
