// Library - DEMO_ALU, Cell - circuit, View - schematic
// LAST TIME SAVED: Mar  4 21:11:28 1999
// NETLIST TIME: Mar  5 18:25:03 1999
`timescale 1ns / 1ns 

module circuit ( cout, out_0_, out_1_, out_2_, out_3_, a_0_, a_1_,
     a_2_, a_3_, accu, b_0_, b_1_, b_2_, b_3_, cin, ck );

output  cout, out_0_, out_1_, out_2_, out_3_;


input  a_0_, a_1_, a_2_, a_3_, accu, b_0_, b_1_, b_2_, b_3_, cin, ck;





specify 
    specparam CDS_LIBNAME  = "DEMO_ALU";
    specparam CDS_CELLNAME = "circuit";
    specparam CDS_VIEWNAME = "schematic";
endspecify

accu_4bits I1 ( out_0_, out_1_, out_2_, out_3_, ck, net101, net100,
     net99, net98);
adder_4bits I0 ( cout, net101, net100, net99, net98, a_0_, a_1_, a_2_,
     a_3_, net55, net54, net53, net52, cin);
mux4 I30 ( net55, net54, net53, net52, b_0_, b_1_, b_2_, b_3_, out_0_,
     out_1_, out_2_, out_3_, accu);

endmodule
