DirLabel =/users/outil3/cadal/hadamar_99/ 
Target Library =hadamard 
Reference Libraries =sample basic ScLib_99 
Verilog Design Files =/users/outil3/cadal/hadamar_99/hadamard.v  
-y Options = 
Library Extn. = 
-v Options = 
-f Options =vlogIn_99.file 
Ignore Modules File = 
Log File =./verilogIn.log 
Work Area =/tmp 
Power Net =vdd! 
Ground Net =gnd! 
Global Signals = 
Import Modules That Match Existing Target Library Cells =false
Verilog Cell Modules =Import
Verilog Structural Modules View =schematic
Functional View Name =functional 
Netlist View Name =netlist 
Schematic View Name =schematic 
Symbol View Name =symbol 
Name Map Table = ./verilogIn.map.table 
Sheet Size =none
Pin Placement Flag =Left and Right Sides
Pin Placement File =
Label Size =0.062500 
Maximum Number Of Rows =1024 
Maximum Number of Columns =1024 
Line-Line Spacing =   0.20000 
Line-Component Spacing =   0.50000 
Density Level =0 
Full Place and Route =true
Fast labels =false
Minimize Cross Over =false
Generate Square Schematics =true
Extract Schematics =true
